A typical example of the digital-to-analog converter circuit is illustrated in FIG. 1 and comprises a high-order digital-to-analog converting stage 1, a low-order digital-to-analog converting stage 2, and a weighted analog adder 3. In operation, high-order m-bits HB1 to HBm of a digital signal are supplied to the input nodes 4 of the high-order digital-to-analog converting stage 1, and low-order n-bits LB1 to LBn of the digital signal are concurrently supplied to the input nodes 5 of the low-order digital-to-analog converting stage 2. Each of the high-order digital-to-analog converting stage 1 and the low-order digital-to-analog converting stage 2 is formed to have a circuit arrangement well-known in the art such as, for example, a resistive ladder, so that no further description will be incorporated.
When the digital signal is applied to the input nodes 4 and the high-order digital-to-analog converting stage 1 is operative to produce a current the amount of which corresponds to a value represented by the high-order bits of the digital signal, likewise the low-order digital-to-analog converting stage 2 is operative to produce a current the amount of which corresponds to a value represented by the low-order bits of the digital signal. The current fed from the high-order digital-to-analog converting stage 1 is added to the current fed from the high-order digital-to-analog converting stage 3 by the analog adder 4, and the current fed from the high-order digital-to-analog converting stage 1 is weighted in the analog adder 3 to have a value which increased by a factor of 2.sup.n with respect to the current fed from the low-order digital-to-analog converting stage 2. The digital-to-analog converter circuit thus arranged produces the total amount of current which corresponds to a value represented by the input digital signal supplied thereto, and the total amount of current is supplied from the output node of the analog adder 3 to an electric circuit (not shown).
However, a problem had been encountered in the prior-art digital-to-analog converter circuit illustrated in FIG. 1 in that the number of bits is limited in view of accuracy of the conversion. In detail, a digital-to-analog converter is allowed to have the driftage of the output current only less than a half of the smallest increment, and the smallest increment is equivalent to the value represented by the least significant bit of the input digital signal. For this reason, the prior-art digital-to-analog converter circuit should have an accuracy of 1/2.sup.m+n.If the input digital signal consists of 8 bits i.e., m=4 and n=4, the accuracy is calculated as 1/2.sup.8 .times.100=0.4%, and, in the case of the 18-bit input digital signal, the accuracy should be 0.0004%. It is impossible to realize these accuracies without any trimming of component element such as the resistive ladder.
One of the approaches to form the digital-to-analog converter circuit without any trimming has been disclosed in Japanese patent application laid-open (Kokai) No. 168522/1982. The circuit arrangement of the digital-to-analog converter circuit disclosed in the Japanese patent application laid-open is illustrated in FIG. 2 of the drawings and largely comprises an input latches 11 for temporary storing an input digital signal, a high-order digital-to-analog converting stage 12 supplied from the input latches 11 with high-order bits of the input digital signal to produce a current corresponding to a value represented by the high-order bits of the input digital signal, a low-order digital-to-analog converting stage 13 supplied from the input latches 11 with low-order bits of the input digital signal to produce a current corresponding to a value represented by the low-order bits, a programmable memory 14 such as an erasable programmable read-only memory storing digital data for error correction, an auxiliary digital-to-analog converting stage 15 supplied from the programmable memory 14 with the digital data and producing a correction current corresponding to the error value inherent in this digital-to-analog converter circuit, an analog adder 16 supplied with the currents fed from the low-order digital-to-analog converter stage 13 and the digital-to-analog converter stage 15 for error correction, and an analog adder 17 supplied with the currents fed from the analog adder 16 and the high-order digital-to-analog converter stage 12 to produce an output current corresponding to a value represented by the input digital signal. The digital-to-analog converter circuit thus arranged is free from the expensive trimming process, because the programmable memory 14 preserves the digital data representative of the error values inherent in that digital-to-analog converter circuit for production of the correction current.
However, another problem is encountered in the digital-to-analog converter circuit disclosed in the above mentioned patent application laid-open in circuit complexity and, accordingly, the number of component element. This is because of the fact that the correction current produced by the digital-to-analog converter stage 15 on the basis of the digital data supplied from the programmable memory 14 is added to the current produced by the low-order digital-to-analog converting stage.